Circuit substrate, manufacturing method thereof and display device

ABSTRACT

The present invention provides a circuit substrate that can reduce Cgd capacitance, sufficiently prevent the influence of Cgd capacitance on applied voltage, together with sufficiently make the reliability of the circuit substrate favorable, to provide a method of manufacturing thereof, and a display device. The circuit substrate of the present invention is a circuit substrate with a semiconductor element arranged on a transparent substrate, in which the semiconductor element is provided with an oxide semiconductor layer; the circuit substrate is provided with an etch-stop layer and a conductive layer, having a region overlapping with neither the etch-stop layer nor the conductive layer, and with at least one portion of the region overlapping with a cutout portion of the oxide semiconductor layer, when the main surface of the circuit substrate is planarly viewed; and a portion of an edge of a cutout portion of the oxide semiconductor layer is located on a side of the etch-stop layer beyond an edge of the etch-stop layer, when the main surface of the circuit substrate is planarly viewed.

TECHNICAL FIELD

The present invention relates to a circuit substrate, method ofmanufacturing thereof, and display device. More particularly, thepresent invention relates to a circuit substrate that can be suitablyused in high resolution display devices and the like, and to a method ofmanufacturing thereof and a display device.

BACKGROUND ART

Circuit substrates have an electric circuit as a constituent element,and circuit substrates containing an element such as a thin filmtransistor (TFT), for example, are widely utilized as components ofelectronic devices such as liquid crystal display devices,electroluminescent display devices, and display devices usingelectrophoresis.

A circuit configuration of a TFT array substrate forming a portion of aTFT driven liquid crystal display panel is described below as anexample. Normally, a TFT array substrate has a pixel circuit containinga structure in which the intersections of wires in an m×n matrixcomposed of scan lines being m rows and signal lines being n columns areprovided with TFTs as switching elements. Note that drain electrode of aTFT is electrically connected to a pixel electrode. Also, peripheralcircuits such as scan driver ICs (integrated circuits) and data driverICs are electrically connected to gate wiring and source wiringextending from each TFT.

The circuits are affected by the performance of TFTs created on the TFTsubstrate. That is, circuits created on a TFT substrate are affected bywhether the circuit is operable, whether the circuit will scale, whetherthe yield will increase, and the like due to the TFTs created on thecircuit substrate, because the performance of the TFTs created on theTFT substrate differ depending on the material quality thereof. Inconventional circuit substrates, a-Si (amorphous silicon) is largelyemployed due to being able to cheaply and easily form TFTs.

Meanwhile, there is disclosed below a method of manufacturing asemiconductor device in which an oxide semiconductor layer is formedinstead of an amorphous silicon semiconductor layer (see Patent Document1, for example).

RELATED ART DOCUMENT Patent Document

-   Patent Document 1: WO 2012/046658

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

Instead of a-Si, there has been research into circuit substrates thathave a semiconductor element with an oxide semiconductor (indium galliumzinc oxide, for example), which is advantageous due to having highmobility, and into a method of manufacturing thereof. The inventors havebeen conducting research that takes into account the reliability ofusing an etch-stop process (hereinafter also referred to as “ESprocess”) in which an etch-stop layer is provided on at least a centerportion of the oxide semiconductor.

There is demand for higher resolution in small-size liquid crystalpanels. The total capacitance of the entirety of a liquid crystal paneldeclines when the resolution of the liquid crystal panel is high and thepixel electrodes are small. Meanwhile, the capacitance between a gateelectrode and a drain electrode (Cgd capacitance) is substantiallyconstant, thus causing the Cgd capacitance to occupy a larger portion oftotal capacitance. Note that Cgd capacitance is basically formed betweena gate metal and a semiconductor layer/source metal via an insulatinglayer.

The Cgd capacitance of a liquid crystal panel using an ES process has atendency to become larger compared to the Cgd capacitance of a liquidcrystal panel using a back-channel-etch system (hereinafter, this typeof liquid crystal panel may be referred to as a “CE structure liquidcrystal panel”). For liquid crystal panels, an ES process is desired inwhich Cgd capacitance can be suitably reduced, thereby reducing theinfluence of Cgd capacitance on applied voltage, appropriatelymaintaining the set voltage, and resulting in favorable displayperformance of a display device provided with a circuit substrate, forexample.

The present invention takes into consideration the above conditions, andan objective thereof is to provide a circuit substrate that can reduceCgd capacitance, sufficiently prevent the influence of Cgd capacitanceon applied voltage, and ensure sufficient reliability of the circuitsubstrate. The present invention also aims a providing a method ofmanufacturing this circuit substrate, and a display device.

Means for Solving the Problems

The inventors conducted various research on patterns and processessuitable for when an ES process is used, from the perspective ofreliability in the production process for oxide semiconductors such asindium gallium zinc oxide, and have discovered how to suitably patternand remove the oxide semiconductor. It was also discovered that oxidesemiconductors can be suitably removed by patterning indium gallium zincoxide using an etchant for a source metal, or in other words, by alsopatterning the oxide semiconductor using wet etching when patterning asource metal using wet etching (that is, the simultaneous patterning ofboth). A configuration was also discovered in which, in circuitsubstrates obtained by this kind of patterning, one portion of an edgeof a removed portion of an oxide semiconductor layer (cutout portion) islocated along an edge of an opening (hole) of an etch-stop layertogether and closer to the etch-stop layer than an edge of the etch-stoplayer, when the main surface of the substrate is planarly viewed,because etching is easy beyond the etch-stop layer in which the oxidesemiconductor layer is configured by insulating material. It wasdiscovered that the above problems can be excellently solved by thiskind of method of manufacturing a circuit substrate and by the circuitsubstrate obtained by this method of manufacturing, thereby leading tothe present invention.

Namely, one aspect of the present invention may be a circuit substratethat includes: a transparent substrate; a semiconductor element disposedon the transparent substrate, the semiconductor element including aoxide semiconductor layer; an etch-stop layer covering at least a centerportion of the oxide semiconductor layer, the etch-stop layer being madeof an insulating material and having an opening therein; and aconductive layer covering at least a portion of the etch-stop layer, thepatterned conductive layer including a source electrode, a source wiringline, and a drain electrode, wherein the circuit substrate has a regionthat does not overlap with both the etch-stop layer and the conductivelayer in a plan view of the substrate surface, a part of this regionoverlapping a cutout portion of the oxide semiconductor layer, andwherein a part of an edge of the cutout portion in the oxidesemiconductor layer is located along an edge of the opening in theetch-stop layer and closer to the etch-stop layer than the edge of theetch-stop layer in a plan view.

The present invention is described in detail below.

It is preferable that another part of an edge of the cutout portion inthe oxide semiconductor layer be located along an edge of the conductivelayer and closer to the conductive layer than the edge of the conductivelayer in a plan view of the substrate surface.

It is preferable that the oxide semiconductor layer include indium,gallium, zinc, and oxide.

It is preferable that the conductive layer be a laminate of at least twolayers, including a layer having at least one selected from a grouphaving aluminum and copper and a layer having at least one selected froma group having titanium, molybdenum, and chromium, and that the layerhaving at least one selected from a group having titanium, molybdenum,and chromium be disposed on a surface side of the conductive layer.

It is preferable that the semiconductor element be a thin filmtransistor.

One aspect of the present invention is a method of manufacturing acircuit substrate constituted of a semiconductor element disposed on atransparent substrate, the method including: forming an island-shapedoxide semiconductor layer; forming a etch-stop layer made of aninsulating material so as to cover at least a center portion of theisland-shaped oxide semiconductor layer; depositing a conductor over theetch-stop layer; and forming a conductive layer from the conductivelayer, wherein the conductive layer includes a source electrode, asource wiring line, and a drain electrode, and simultaneously patterningthe island-shaped oxide semiconductor layer, and forming the oxidesemiconductor layer with to form a cutout in the island-shaped oxidesemiconductor layer.

It is preferable that wet-etching with the same etchant be used informing the conductive layer and in forming the oxide semiconductorlayer.

It is preferable that the method of manufacturing a circuit substratefurther include, after forming the conductive layer and forming theoxide semiconductor layer, forming an insulating layer.

One aspect of the present invention may be a circuit substrate made bythe method of manufacturing a circuit substrate.

One aspect of the present invention may be a display device thatincludes: the circuit substrate.

Effects of the Invention

The circuit substrate of the present invention can reduce Cgdcapacitance, sufficiently prevent the influence of Cgd capacitance onapplied voltage, together with sufficiently ensuring the reliability ofthe circuit substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 1.

FIG. 2 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after formation ofan etch-stop layer.

FIG. 3 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line C-D of FIG. 1 after formation ofan etch-stop layer.

FIG. 4 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line E-F of FIG. 1 after formation ofan etch-stop layer.

FIG. 5 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after formation ofa conductive layer and an oxide semiconductor layer.

FIG. 6 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line C-D of FIG. 1 after formation ofa conductive layer and an oxide semiconductor layer.

FIG. 7 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line E-F of FIG. 1 after formation ofa conductive layer and an oxide semiconductor layer.

FIG. 8 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after depositionof a protective film.

FIG. 9 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line C-D of FIG. 1 after depositionof a protective film.

FIG. 10 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line E-F of FIG. 1 after depositionof a protective film.

FIG. 11 is a schematic cross-sectional view taken along the line A-B ofFIG. 1.

FIG. 12 is a schematic cross-sectional view taken along the line C-D ofFIG. 1.

FIG. 13 is a schematic cross-sectional view taken along the line E-F ofFIG. 1.

FIG. 14 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 2.

FIG. 15 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 3.

FIG. 16 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 4.

FIG. 17 is a schematic cross-sectional view illustrating a configurationafter formation of a gate corresponding to a TFT portion of a circuitsubstrate of a modification example of Embodiment 1.

FIG. 18 is a schematic cross-sectional view illustrating a configurationafter formation of an oxide semiconductor layer corresponding to a TFTportion of a circuit substrate of a modification example of Embodiment1.

FIG. 19 is a schematic cross-sectional view illustrating a configurationafter formation of an etch-stop layer corresponding to a TFT portion ofa circuit substrate of a modification example of Embodiment 1.

FIG. 20 is a schematic cross-sectional view illustrating a configurationafter formation of a conductive layer corresponding to a TFT portion ofa circuit substrate of a modification example of Embodiment 1.

FIG. 21 is a schematic cross-sectional view illustrating a configurationafter formation of protective film and organic insulation filmcorresponding to a TFT portion of a circuit substrate of a modificationexample of Embodiment 1.

FIG. 22 is a schematic cross-sectional view illustrating a configurationafter formation of pixel electrodes corresponding to a TFT portion of acircuit substrate of a modification example of Embodiment 1.

FIG. 23 is a schematic cross-sectional view illustrating a configurationafter formation of a common electrode corresponding to a TFT portion ofa circuit substrate of another modification example of Embodiment 1.

FIG. 24 is a schematic cross-sectional view illustrating a configurationafter formation of protective film corresponding to a TFT portion of acircuit substrate of the other modification example of Embodiment 1.

FIG. 25 is a schematic cross-sectional view illustrating a configurationafter formation of pixel electrodes corresponding to a TFT portion of acircuit substrate of the other modification example of Embodiment 1.

FIG. 26 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Comparison Example 1.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments are described below, and the present invention is furtherdescribed in detail with reference to figures, but the present inventionis not limited to only these embodiments.

In the specifications, “provided on a member (layer)” refers to “atleast one portion thereof provided on a display element side of themember”. It is preferable that “an opening of an etch-stop layer” be “athrough-hole of an etch-stop layer,” and its shape not be particularlylimited. Also, the periphery of an opening may be completely enclosed ornot completely enclosed by an etch-stop layer. Moreover, as long as acutout portion of an oxide semiconductor layer is provided correspondingto at least one portion of a region overlapping with neither anetch-stop layer nor the conductive layer, its shape is not particularlylimited. Patterning refers to forming a layer or film to be formed bycoating the entirety of a substrate deposited with the layer or film tobe formed with a photosensitive resist and the like, forming a resistpattern by lithographically exposing the resist and the like, removingthe layer or film to be formed and exposed from the resist pattern byetching, and then stripping the resist pattern, for example. Highresolution refers to 300 dpi (dots per inch) or above, for example.

Embodiment 1

FIG. 1 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 1. The circuit substrateof Embodiment 1 has a semiconductor element arranged on a transparentsubstrate. The semiconductor element has an oxide semiconductor layer IGof indium gallium zinc oxide and the like. For the circuit substrate, anetch-stop layer constituted of an insulating material is arranged suchthat at least a center portion of the oxide semiconductor layer iscovered. Also, the circuit substrate is provided with a conductive layerS constituted by source electrodes, source wires, and drain electrodes,with at least one portion thereof arranged on the etch-stop layer. Theetch-stop layer is provided with openings H. In FIG. 1, the etch-stoplayer is the portions that are not rectangular areas surrounded by theopenings H.

The circuit substrate has a region overlapping with neither theetch-stop layer nor the conductive layer S when the main surface of thecircuit substrate is seen in a plan view. At least one portion of thisregion is a cutout portion Cut of the oxide semiconductor layer IG.

When the circuit substrate is used in a display device provided with alight source, for example, an electric charge accumulates in the oxidesemiconductor and the display reliability worsens due to the influenceof the backlight and the like. There were also cases in which the Cgdcapacitance increased. Oxide semiconductors of indium gallium zinc oxideand the like are weak to photoreactions; thus, it is desirable that itsarea be shrunk as much as possible. Meanwhile, as shown by the presentembodiment, an oxide semiconductor can be patterned and the Cgdcapacitance thereof reduced by removing one portion of the oxidesemiconductor. An illustration is omitted from FIG. 1, but as will beevident from a cross-sectional view described hereinafter, only 0.5 μmto 1.5 μm, for example, of one portion of an edge of a cutout portionCut of the oxide semiconductor layer is located along an edge of anopening H of the etch-stop layer and is closer to the etch-stop layerthan an edge of the etch-stop layer itself.

In a plan view of the substrate surface, the edges of the cut-out in theoxide semiconductor layer that are along the opening in the etch stoplayer do not need to be completely under the edges of the etch stoplayer, but may instead be substantially under these edges

Also, as is evident from the figure, only 0.5 μm to 1.5 μm, for example,of other portions of the edges of the cutout portion Cut of the oxidesemiconductor layer are located along an edge of the conductive layer Sinside the conductive layer S and further away from an edge of theconductive layer S, when the main surface of the substrate is planarlyviewed.

It is preferable that the portion located along an edge of theconductive layer S within an edge of the cutout portion Cut of the oxidesemiconductor layer be substantially located on inside the conductivelayer S away from an edge of the conductive layer S, without the need tobe completely located on the side of the conductive layer S beyond anedge of the conductive layer S, when the main surface of the circuitsubstrate is planarly viewed.

A manufacturing process for the circuit substrate of Embodiment 1 isdescribed in detail below.

FIG. 2 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after formation ofan etch-stop layer. FIG. 3 is a schematic cross-sectional view of asubstrate corresponding to a cross-section taken along the line C-D ofFIG. 1 after formation of an etch-stop layer. FIG. 4 is a schematiccross-sectional view of a substrate corresponding to a cross-sectiontaken along the line E-F of FIG. 1 after formation of an etch-stoplayer.

First, gate wiring G is formed on a transparent substrate such as aglass substrate. Forming the gate wiring G can be conducted by forming awiring layer, and then, patterning to a desired shape usingphotolithography, for example. Specifically, a resist is formed using amask process and etching is conducted on the wiring layer to form thegate wiring. Next, the resist is removed.

Next, a gate insulation film GI is formed. The gate insulation film GImay be a film of silicon nitride (SiN_(x)), silicon oxide (SiO₂), or thelike, and can be formed using plasma enhanced chemical vapor deposition(PECVD), for example.

Next, an island-shaped oxide semiconductor layer IG of indium galliumzinc oxide or the like is formed. The island-shaped oxide semiconductorcan be formed by depositing an oxide semiconductor IG material with alayer thickness of 10 nm to 300 nm using sputtering, forming the film,and then patterning to a desired shape using photolithography, forexample.

Next, the etch-stop layer ES is formed. For the etch-stop layer ES, aninsulating film with a film thickness of 50 nm to 300 nm is formed byplasma enhanced CVD (chemical vapor deposition) using an insulatingmaterial such as an insulating material containing silicon (siliconoxide film (SiO₂), silicon nitride film (SiN_(x)), and silicon nitrideoxide film (SiNO), for example) or sputtering, and then, a resist isformed using a mask process, and etching is conducted on the insulatingfilm to form an etch-stop layer provided with an opening H, for example.Also, the etch-stop layer ES is formed such that at least a centerportion of the island-shaped oxide semiconductor IG is covered. Next,the resist is removed. The etch-stop layer ES is added in this manner inorder to maintain the reliability of the circuit substrate with theproduced oxide semiconductor layer IG.

The etch-stop layer ES is provided with two openings H and configuredsuch that a center portion of the oxide semiconductor layer IG isarranged between the two openings H in a plan view, for example.

FIG. 5 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after formation ofa conductive layer and an oxide semiconductor layer. FIG. 6 is aschematic cross-sectional view of a substrate corresponding to across-section taken along the line C-D of FIG. 1 after formation of aconductive layer and an oxide semiconductor layer. FIG. 7 is a schematiccross-sectional view of a substrate corresponding to a cross-sectiontaken along the line E-F of FIG. 1 after formation of a conductive layerand an oxide semiconductor layer.

A conductor is deposited on the etch-stop layer ES. A resist is formedusing a mask process and etching is conducted on the conductor and theisland-shaped oxide semiconductor IG. That is, the conductive layer Sconstituted of source electrodes, source wiring, and drain electrodesfrom the conductor is formed and the oxide semiconductor layer IG havinga cutout portion is formed by patterning the conductor using wet etchingand the like, and during this, also simultaneously patterning theisland-shaped oxide semiconductor IG (see FIGS. 6 and 7, for example).In other words, a portion of the island-shaped oxide semiconductor isremoved at the same time that the conductor is patterned to form theconductive layer S, which is constituted of source electrodes, sourcewiring, and drain electrodes. Next, the resist on the substrate isremoved.

It is preferable that the formation of the conductive layer and theoxide semiconductor layer be conducted using wet etching. It is alsopossible to cut the manufacturing cost of the circuit substrate bypatterning using wet etching. For an etchant used in wet etching, thesame etchants used in wet etching for source metals may be suitablyused, and suitable examples include peroxide based etchants (used onsource metals being Cu/Ti laminates, referring to the Cu being the toplayer and the Ti being the bottom layer/general etchant for Cu, mixedsolution of phosphate+nitrate+acetate, used on source metals and thelike being Mo/Al/Mo laminate/general etchant for Al), and the like.Thereby, even when the source metal is a laminate, the source metal canbe etched all at once.

Thus, as illustrated in FIG. 1, a portion of an edge of a cutout portionCut of the oxide semiconductor layer IG is located along an edge of anopening H of the etch-stop layer ES, when the main surface of thecircuit substrate is planarly viewed. Also, as illustrated in FIG. 1,one portion of an edge of a cutout portion Cut of the oxidesemiconductor layer IG is located closer to the etch-stop layer ES thanan edge of the etch-stop layer ES (the oxide semiconductor layer IG istucked under the etch-stop layer ES), when the main surface of thecircuit substrate is planarly viewed. The etch-stop layer ES has anopening H, and there is no oxide semiconductor layer IG, and there is aportion with the conductive layer S.

Moreover, as illustrated in FIG. 1, the other portions of an edge of acutout portion Cut of the oxide semiconductor layer IG are located alongan edge of the conductive layer S when the main surface of the circuitsubstrate is planarly viewed. Also, as illustrated in FIG. 1, the otherportions of an edge of a cutout portion Cut of the oxide semiconductorlayer IG are located closer to the conductive layer S than an edge ofthe conductive layer S (the oxide semiconductor layer IG tucked underthe conductive layer S).

A pattern for the oxide semiconductor layer IG may be formed using theetch-stop layer ES and a source, and reduction of Cgd and improvement ofthe reliability of the circuit substrate may both be achieved byremoving a portion of the oxide semiconductor layer IG.

FIG. 8 is a schematic cross-sectional view of a substrate correspondingto a cross-section taken along the line A-B of FIG. 1 after formation ofa protective film deposit. FIG. 9 is a schematic cross-sectional view ofa substrate corresponding to a cross-section taken along the line C-D ofFIG. 1 after formation of a protective film deposit. FIG. 10 is aschematic cross-sectional view of a substrate corresponding to across-section taken along the line E-F of FIG. 1 after formation of aprotective film deposit.

A protective film PAS1 is formed. The protective film PAS1 may be asilicon nitride (SiN_(x)) film, silicon oxide (SiO₂) film, or the like,and may be formed by plasma enhanced chemical vapor deposition (PECVD)or the like, for example. Note that in FIG. 9 a condition is illustratedin which the oxide semiconductor layer IG is tucker under the etch-stoplayer ES, and in FIG. 10 a condition is illustrated in which the oxidesemiconductor layer IG is tucked under the conductive layer (sourcemetal) S.

FIG. 11 is a schematic cross-sectional view taken along the line A-B ofFIG. 1. FIG. 12 is a schematic cross-sectional view taken along the lineC-D of FIG. 1. FIG. 13 is a schematic cross-sectional view taken alongthe line E-F of FIG. 1.

First, an organic insulating film OI is formed. The organic insulatingfilm OI may be an acrylic resin, and may be formed by spin coating andthe like, for example. Note that, as illustrated in FIGS. 11 to 13, thesubstrate can be planarized by forming the organic insulating film OI.

Next, a common electrode Com is formed on the entire surface of theorganic insulating film OI. The common electrode Com can be composed ofITO (Indium Tin Oxide) but may also be composed of other transparentelectrodes such as IZO (Indium Zinc Oxide) instead of ITO.

Next, a protective film PAS2 is formed on the entire surface of thecommon electrode Com. In a similar manner to the protective film PAS1,the protective film PAS2 may be a silicon nitride (SiN_(x)) film or thelike, and may be formed by plasma enhanced chemical vapor deposition(PECVD) or the like, for example.

Next, pixel electrodes Pix are formed on the entire surface of theprotective film PAS2. The common electrode Com can be composed of ITO(Indium Tin Oxide) but may also be composed of other transparentelectrodes such as IZO (Indium Zinc Oxide) instead of ITO.

A portion of the island-shaped oxide semiconductor IG of a regionoverlapping with neither the etch-stop layer nor the conductive layer Sis removed by the formation of the aforementioned conductive layer andthe oxide semiconductor layer. Thereby, Cgd can be reduced between theoxide semiconductor layer IG with a cutout portion and the conductivelayer.

Members and the like described in the aforementioned manufacturingprocess of the circuit substrate of Embodiment 1 are described in detailbelow.

The conductive layer S is configured by a source metal. “Source metal”refers to source wiring and members (source electrodes, drainelectrodes, and the like) formed using a process the same as for thesource wiring.

“Conductive layer S” refers to a Cu/Ti laminate or a Mo/Al/Mo laminate,but objects containing, besides the above, an aluminum layer, analuminum alloy layer, a copper layer, and/or a copper alloy layer may besuitably used.

The aluminum layer is a layer substantially configured by only aluminummetal. In the manufacturing of wiring containing an aluminum layer,there are cases in which trace amounts of impurity elements arecontained in the aluminum layer, because elements also scatter fromother metal materials, interlayer insulating films, and the like incontact with the aluminum layer. Also, the aluminum alloy layer maycontain aluminum as necessary, and may be configured by containing othermetallic elements and nonmetallic elements such as silicon. Examples ofthe metallic elements added to the aluminum alloy include nickel, iron,cobalt, and the like. It is more preferable to further add boron,neodymium, lanthanum, and the like as an additional element to thealuminum alloy.

The copper layer is a layer substantially configured by only copper. Forthe copper layer, there are cases in which trace amounts of impurityelements are contained therein, because elements also scatter from othermetal materials, interlayer insulating films, and the like in contactwith the copper layer. The copper alloy layer may contain copper asnecessary, and may be further configured by containing other metallicelements and nonmetallic elements such as carbon and silicon. Examplesof the metallic elements added to the copper alloy include magnesium,manganese, and the like.

Other metallic elements may be suitably used as the conductive layer S.

The wires are signal wires transmitting an electric signal, power supplywires for supplying power, wires configuring a circuit, wires forapplying an electric field (applying an electric field to a TFT gate,for example), and the like. Also, when applying the circuit substrate ofthe present invention to a liquid crystal display device, the circuitsubstrate of the present invention may be further provided withauxiliary capacitance wiring for forming auxiliary capacitance used forretaining voltage applied to the liquid crystals.

It is preferable that the semiconductor element be a thin filmtransistor (TFT). When using the TFT on an active matrix substrate for adisplay device, for example, the source wiring is electrically incontact with pixel electrodes, which the display pixels configure, viasource electrodes and drain electrodes, which the TFT configures.

For the transparent substrate, various substrates may be used withoutbeing particularly limited. Substrates such as single crystalsemiconductor substrates, oxide single crystal substrates, metalsubstrates, glass substrates, quartz substrates, and resin substrates,for example, may be used. In the case of a single crystal semiconductorsubstrate or a conductive substrate such as a metal substrate, forexample, it is preferable that these substrates be used by providing aninsulating film and the like thereon.

For the aforementioned gate insulation film, etch-stop layer, protectivefilm, organic insulating film, and the like, there may be 1 or morelayers.

It is preferable that the pixel electrodes be a transparent conductivefilm. Normally, Indium Tin Oxide, Indium Zinc Oxide, and the like areused as a transparent conductive film and thus may be suitably used inthe circuit substrate of the present invention.

The circuit substrate according to Embodiment 1 may be disassembled andshapes of the liquid crystal cells and the like may be verified byobservation with a microscope such as an optical microscope, scanningtransmission electron microscope (STEM), and scanning electronmicroscope (SEM).

The circuit substrate of Embodiment 1, as mentioned above, cansufficiently make the reliability of a circuit substrate favorable andsufficiently reduce Cgd capacitance, because the etch-stop layer isprovided. Also, the circuit substrate of Embodiment 1 may be the easiestto manufacture. Particularly for high resolution display devices, thecircuit substrate of Embodiment 1 is suitable for cutting ΔVd (pull-involtage).

The circuit substrate of Embodiment 1 was bonded with a substrateopposed thereto, and a liquid crystal display panel was manufactured byinjecting liquid crystals. Also, this became a liquid crystal displaydevice by providing the liquid crystal display panel with a polarizingplate and other members thereof.

Embodiment 2

FIG. 14 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 2.

The shape of the oxide semiconductor IG according to Embodiment 2differs from the shape of the oxide semiconductor conductor IG accordingto Embodiment 1. For the oxide semiconductors IG according toEmbodiments 1 and 2, both the widths W of the center portions are thesame as the widths of the gate wiring G, and the width of both ends arelarger than the widths W of the center portions. Here, for the width ofboth ends, the width for Embodiment 2 is smaller than the width forEmbodiment 1. Also, in Embodiment 2, a portion of the left end of theoxide semiconductor layer IG within FIG. 14 does not overlap with theconductive layer S (source wiring) extending in a vertical direction.The other configurations of Embodiment 2 are the same as theaforementioned configurations of Embodiment 1. For the circuit substrateof Embodiment 2, manufacturing is not as easy as with Embodiment 1, butCgd capacitance can be reduced more.

Embodiment 3

FIG. 15 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 3. The openings H of theetch-stop layer according to Embodiment 3 are smaller in a verticaldirection on FIG. 15 than the openings H of the etch-stop layeraccording to Embodiment 1. The other configurations of Embodiment 3 arethe same as the aforementioned configurations of Embodiment 1. For thecircuit substrate of Embodiment 3, manufacturing is not as easy as withEmbodiment 2, but Cgd capacitance can be reduced more.

Embodiment 4

FIG. 16 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Embodiment 4. The openings H of theetch-stop layer according to Embodiment 4 are smaller in a verticaldirection on FIG. 15 than the openings H of the etch-stop layeraccording to Embodiment 2. The other configurations of Embodiment 4 arethe same as the aforementioned configurations of Embodiment 1. For thecircuit substrate of Embodiment 4, manufacturing is not as easy as withEmbodiment 3, but Cgd capacitance can be reduced more.

A structure of a TFT portion that can suitably apply the presentinvention is described in detail below. The configurations besides theones specified below are the same as the aforementioned configurationsfor Embodiment 1.

Modification Example of Embodiment 1

FIG. 17 is a schematic cross-sectional view illustrating a configurationafter formation of a gate corresponding to a TFT portion of a circuitsubstrate of a modification example of Embodiment 1. First, gate wiringG was formed on a transparent substrate such as a glass substrate. It ispreferable that the gate wiring G be a Cu/Ti laminate or a TiN/Ti/AIlaminate, for example.

FIG. 18 is a schematic cross-sectional view illustrating a configurationafter formation of an oxide semiconductor layer corresponding to a TFTportion of a circuit substrate of a modification example ofEmbodiment 1. A gate insulation film GI was further formed from thesubstrate illustrated in FIG. 17. Next, an island-shaped oxidesemiconductor layer IG of indium gallium zinc oxide and the like wasformed.

FIG. 19 is a schematic cross-sectional view illustrating a configurationafter formation of an etch-stop layer corresponding to a TFT portion ofa circuit substrate of a modification example of Embodiment 1. Anetch-stop layer ES was further formed from the substrate illustrated inFIG. 18.

FIG. 20 is a schematic cross-sectional view illustrating a configurationafter formation of a conductive layer corresponding to a TFT portion ofa circuit substrate of a modification example of Embodiment 1. Aconductive layer S was further formed on the etch-stop layer ES from thesubstrate illustrated in FIG. 19. It is preferable that the conductivelayer S be a Cu/Ti laminate or a MoN/Al/Mon laminate, for example.Liquid medicine that can etch the conductive layer S and the oxidesemiconductor layer IG was used as an etchant for wet etching.

FIG. 21 is a schematic cross-sectional view illustrating a configurationafter formation of protective film and organic insulation filmcorresponding to a TFT portion of a circuit substrate of a modificationexample of Embodiment 1. A protective film PAS1 was further formed fromthe substrate illustrated in FIG. 20. Next, an organic insulating filmOI was formed.

FIG. 22 is a schematic cross-sectional view illustrating a configurationafter formation of pixel electrodes corresponding to a TFT portion of acircuit substrate of a modification example of Embodiment 1. Pixelelectrodes Pix were further formed on the entire surface of the organicinsulating film OI from the substrate illustrated in FIG. 21. The pixelelectrodes Pix can be composed of ITO (Indium Tin Oxide) but may also becomposed of other transparent electrodes such as IZO (Indium Zinc Oxide)instead of ITO.

The modification example of the circuit substrate of Embodiment 1 may besuitably used in liquid crystal display devices in a vertical alignment(VA) mode.

Another Modification Example of Embodiment 1

The other modification example of Embodiment 1 is the same as theaforementioned modification example of Embodiment 1 up to the formationof the organic insulating film. The steps after formation of the organicinsulating film are described below. Note that the configurationsbesides the ones specified for each member (materials and the like) arethe same as the aforementioned configurations.

FIG. 23 is a schematic cross-sectional view illustrating a configurationafter formation of common electrodes corresponding to a TFT portion of acircuit substrate of the other modification example of Embodiment 1.Electrode materials were deposited on the entire surface of the organicinsulating film OI and patterning was conducted to form commonelectrodes Com.

FIG. 24 is a schematic cross-sectional view illustrating a configurationafter formation of protective film corresponding to a TFT portion of acircuit substrate of the other modification example of Embodiment 1. Aprotective film PAS2 was further formed on the common electrodes Comfrom the substrate illustrated in FIG. 23.

FIG. 25 is a schematic cross-sectional view illustrating a configurationafter formation of pixel electrodes corresponding to a TFT portion of acircuit substrate of the other modification example of Embodiment 1.From the substrate illustrated in FIG. 24, electrode materials werefurther deposited on the entire surface of the protective film PAS2 andpatterning was conducted to form pixel electrodes Pix.

The other modification example of the circuit substrate of Embodiment 1may be suitably used in liquid crystal display devices in a fringe fieldswitching (FFS) mode.

Comparison Example 1

FIG. 26 is a schematic plan view illustrating a configuration of a TFTportion of the circuit substrate of Comparison Example 1.

For the circuit substrate illustrated in FIG. 26, the entirety of theopenings H of the etch-stop layer ES is located on the inner side of theconductive layer S, when the main surface of the substrate is planarlyviewed. In other words, for the circuit substrate illustrated in FIG.26, there are no regions overlapping with neither the etch-stop layer ESnor the conductive layer S. Because of this, in Comparison Example 1,the oxide semiconductor layer IG is not patterned during wet etching ofthe conductive layer S. Accordingly, Cgd capacitance cannot besufficiently reduced. Note that other configurations of the circuitsubstrate of Comparison Example 1 and manufacturing processes are thesame as those aforementioned in Embodiment 1.

Other Embodiments

The semiconductor elements of the aforementioned embodiments refer to3-terminal elements such as transistors, but it is possible to use2-terminal elements and the like such as diodes as conductor elements.

As an oxide semiconductor layer, an oxide semiconductor configured byIn, Si, Zn, and O, an oxide semiconductor configured by In, Al, Zn, andO, an oxide semiconductor configured by Sn, Si, Zn, and O, an oxidesemiconductor configured by Sn, Al, Zn, and O, an oxide semiconductorconfigured by Sn, Ga, Zn, and O, an oxide semiconductor configured byGa, Si, Zn, and O, an oxide semiconductor configured by Ga, Al, Zn, andO, an oxide semiconductor configured by In, Cu, Zn, and O, an oxidesemiconductor configured by Sn, Cu, Zn, and O, an oxide semiconductorconfigured by Zn and O, an oxide semiconductor configured by In and O,and the like may be used besides indium gallium zinc oxide.

For the aforementioned embodiments, a gate wiring G, gate insulatingfilm GI, and oxide semiconductor layer IG are formed in this order on atransparent substrate, and a back gate thin film transistor in which theconductive layer S is in contact with the oxide semiconductor layer IGis formed, but the present invention may also be suitably applied to topgate thin film transistors.

Each circuit substrate of the embodiments is suitably used in displaydevices such as liquid crystal display devices, organic EL displaydevices, and inorganic EL display devices as an active matrix substrate,but is not limited to a circuit substrate for a display device.

The technical features described in each embodiment can be mutuallycombined, and can form a new technical feature by being combined. InEmbodiment 1, a configuration is illustrated in which common electrodesand pixel electrodes are provided on a circuit substrate, but as isillustrated in the modification example of Embodiment 1, a configurationmay be set in which only pixel electrodes are provided and commonelectrodes are not provided, for example.

DESCRIPTION OF REFERENCE CHARACTERS

-   -   Com common electrode    -   Cut cutout portion of oxide semiconductor layer    -   ES etch-stop layer    -   G gate wiring    -   GI gate insulation film    -   H opening of etch-stop layer    -   IG island-shaped oxide semiconductor or oxide semiconductor        layer    -   OI organic insulating film    -   L distance between two openings provided on etch-stop layer    -   PAS1, PAS2 protective film    -   Pix pixel electrodes    -   S conductive layer    -   W width of central portion of oxide semiconductor layer

1. A circuit substrate comprising: a transparent substrate; asemiconductor element disposed on the transparent substrate, saidsemiconductor element including a patterned oxide semiconductor layer;an etch-stop layer covering at least a center portion of the oxidesemiconductor layer, the etch-stop layer being made of an insulatingmaterial and having an opening therein; and a patterned conductive layercovering at least a portion of the etch-stop layer, the patternedconductive layer including a source electrode, a source wiring line, anda drain electrode, wherein a part of an edge of the oxide semiconductorlayer is defined by an edge of the opening in the etch-stop layer and istucked under said edge of the etch-stop layer.
 2. The circuit substrateaccording to claim 1, wherein another part of an edge of the oxidesemiconductor layer is defined by an edge of the patterned conductivelayer and is tucked under said edge of the patterned conductive layer.3. The circuit substrate according to claim 1, wherein the oxidesemiconductor layer comprises indium, gallium, zinc, and oxide.
 4. Thecircuit substrate according to claim 1, wherein the patterned conductivelayer is a laminate of at least two layers, including a layer having atleast one selected from a group comprising aluminum and copper and alayer having at least one selected from a group comprising titanium,molybdenum, and chromium, and wherein the layer having at least oneselected from a group comprising titanium, molybdenum, and chromium isdisposed on a surface side of the conductive layer.
 5. The circuitsubstrate according to claim 1, wherein the semiconductor element is athin film transistor.
 6. A method of manufacturing a circuit substratecomprising a semiconductor element disposed on a transparent substrate,said method comprising: forming an island-shaped oxide semiconductorlayer on the transparent substrate; forming a patterned etch-stop layermade of an insulating material so as to cover at least a center portionof the island-shaped oxide semiconductor layer; depositing a conductivelayer over an entire surface of the transparent substrate including aregion over the patterned etch-stop layer; forming a patterned resist onthe conductive layer; and etching the conductive layer using thepatterned resist as a mask to form a patterned conductive layer from theconductive layer, wherein the patterned conductive layer includes asource electrode, a source wiring line, and a drain electrode, andcontinuing to etch the island-shaped oxide semiconductor thereunderusing the patterned conductive layer and the patterned etch-stop layeras a mask to form a cutout in the island-shaped oxide semiconductorlayer.
 7. The method of manufacturing a circuit substrate according toclaim 6, wherein wet-etching with the same etchant is used in etchingthe conductive layer and in etching the island-shaped oxidesemiconductor layer underneath.
 8. The method of manufacturing a circuitsubstrate according to claim 6, further comprising, after forming thepatterned conductive layer and forming the cutout in the island-shapedoxide semiconductor layer, forming an insulating layer.
 9. A circuitsubstrate made by the method of manufacturing a circuit substrateaccording to claim 6, the circuit substrate comprising: the transparentsubstrate; the semiconductor element disposed on the transparentsubstrate, said semiconductor element including the patterned oxidesemiconductor layer; the etch-stop layer covering at least the centerportion of the oxide semiconductor layer, the etch-stop layer having anopening therein; and the patterned conductive layer covering at least aportion of the etch-stop layer, the patterned conductive layer includingthe source electrode, the source wiring line, and the drain electrode,wherein an edge of the cutout of the oxide semiconductor layer isdefined by an edge of the opening in the etch-stop layer and is tuckedunder said edge of the etch-stop layer.
 10. A display device,comprising: the circuit substrate according to claim 1; and an oppositesubstrate coupled to the circuit substrate.
 11. The method ofmanufacturing a circuit substrate according to claim 6, wherein theisland-shaped oxide semiconductor layer comprises indium, gallium, zinc,and oxide.